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EN25QH32-104QIP 参数 Datasheet PDF下载

EN25QH32-104QIP图片预览
型号: EN25QH32-104QIP
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆位串行闪存与4K字节扇区制服 [32 Megabit Serial Flash Memory with 4Kbyte Uniform Sector]
分类和应用: 闪存
文件页数/大小: 63 页 / 1168 K
品牌: EON [ EON SILICON SOLUTION INC. ]
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EN25QH32  
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used  
as an extra software protection mechanism, when the device is not in active use, to protect the device  
from inadvertent Write, Program or Erase instructions.  
Status Register  
The Status Register contains a number of status and control bits that can be read or set (as appropriate)  
by specific instructions.  
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status  
Register, Program or Erase cycle.  
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.  
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define  
the size of the area to be software protected against Program and Erase instructions.  
QE bit. The Quad Enable (QE) bit, non-volatile bit, enable bit only for Quad Input/Output FAST_READ  
(EBh) in SPI command. When it is “0” (factory default), it disables Quad Input/Output FAST_READ  
(EBh) in SPI command and WP#, HOLD# are enabled. While QE is “1”, it enables Quad Input/Output  
FAST_READ (EBh) in SPI command and WP#, HOLD# are disabled. In other words, in SPI mode, the  
QE bit needs to be assigned through WRSR to enable or disable SPI command Quad Input/Output  
FAST_READ (EBh). If the system goes into Full Quad I/O (EQPI), this QE bit becomes no affection  
since WP# and HOLD# function will be disabled by EQPI mode and Quad Input/Output FAST_READ  
(EBh) will be always available in EQPI mode.  
SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit operates in conjunction with the Write  
Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the  
device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status  
Register (SRP, BP3, BP2, BP1, BP0) become read-only bits.  
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal  
sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR  
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only  
be programmed once.  
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,  
user must clear the protect bits before entering OTP mode and program the OTP code, then execute  
WRSR command to lock the OTP sector before leaving OTP mode.  
Write Protection  
Applications that use non-volatile memory must take into consideration the possibility of noise and other  
adverse system conditions that may compromise data integrity. To address this concern the  
EN25QH32 provides the following data protection mechanisms:  
z
Power-On Reset and an internal timer (t ) can provide protection against inadvertent changes  
PUW  
while the power supply is outside the operating specification.  
z
z
Program, Erase and Write Status Register instructions are checked that they consist of a number  
of clock pulses that is a multiple of eight, before they are accepted for execution.  
All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set  
the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:  
– Power-up  
Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction  
completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction  
completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction  
completion  
z
z
z
The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as read-  
only. This is the Software Protected Mode (SPM).  
The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status  
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).  
In addition to the low power consumption feature, the Deep Power-down mode offers extra  
software protection from inadvertent Write, Program and Erase instructions, as all instructions are  
ignored except one particular instruction (the Release from Deep Power-down instruction).  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc., www.eonssi.com  
11  
Rev. E, Issue Date: 2012/01/30