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EN25P05-100GI 参数 Datasheet PDF下载

EN25P05-100GI图片预览
型号: EN25P05-100GI
PDF下载: 下载PDF文件 查看货源
内容描述: 512 Kbit的统一部门,串行闪存 [512 Kbit Uniform Sector, Serial Flash Memory]
分类和应用: 闪存
文件页数/大小: 30 页 / 377 K
品牌: EON [ EON SILICON SOLUTION INC. ]
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EN25P05  
Deep Power-down (DP) (B9h)  
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest con-  
sumption mode (the Deep Power-down mode). It can also be used as an extra software protection  
mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program  
and Erase instructions.  
Driving Chip Select (CS#) High deselects the device, and puts the device in the Standby mode (if there is  
no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep  
Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce  
the standby current (from ICC1 to ICC2, as specified in Table 8.).  
Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release  
from Deep Power-down and Read Device ID (RDI) instruction. This releases the device from this mode.  
The Release from Deep Power-down and Read Device ID (RDI) instruction also allows the Device ID of  
the device to be output on Serial Data Output (DO).  
The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the  
Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (CS#) Low,  
followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the  
entire duration of the sequence.  
The instruction sequence is shown in Figure 14..Chip Select (CS#) must be driven High after the eighth bit  
of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not  
executed. As soon as Chip Select (CS#) is driven High, it requires a delay of t before the supply current  
DP  
is reduced to ICC2 and the Deep Power-down mode is entered.  
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected  
without having any effects on the cycle that is in progress.  
Release from Deep Power-down and Read Device ID (RDI)  
Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release  
from Deep Power-down and Read Device ID (RDI) instruction. Executing this instruction takes the device  
out of the Deep Power-down mode.  
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that  
is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for  
reasons of backward compatibility, only, and should not be used for new designs. New designs should,  
instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction.  
When used only to release the device from the power-down state, the instruction is issued by driving the  
CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 15. After the  
time duration of t  
(See AC Characteristics) the device will resume normal operation and other  
RES1  
instructions will be accepted. The CS# pin must remain high during the t  
time duration.  
RES1  
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by  
driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID  
bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc., www.essi.com.tw  
16  
Rev. B, Issue Date: 2006/12/27