EN25D16
(4)
Release from Deep
Power-down, and
read Device ID
Release from Deep
Power-down
dummy
dummy
dummy
dummy (ID7-ID0)
ABh
90h
Manufacturer/
Device ID
(5)
00h
dummy
(M7-M0)
(ID7-ID0)
(ID15-
ID8)
(ID7-
ID0)
Read Identification
Enter OTP mode
9Fh
3Ah
(M7-M0)
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from
the device on the DO pin.
2. The Status Register contents will repeat continuously until CS# terminate the instruction.
3. All sectors may use any address within the sector.
4. The Device ID will repeat continuously until CS# terminate the instruction.
5. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.
Table 5. Manufacturer and Device Identification
OP Code
ABh
(M7-M0)
(ID15-ID0)
(ID7-ID0)
14h
90h
1Ch
1Ch
14h
9Fh
3015h
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit. The Write
Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block
Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the
instruction code, and then driving Chip Select (CS#) High.
Figure 5. Write Enable Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
11
Rev. B, Issue Date: 2008/06/23
EON [ EON SILICON SOLUTION INC. ]
