EN5322QI
applications for minimal current drain from the
voltage source and good noise immunity. POK
can sink up to 5mA.
If the external voltage divider option is chosen,
use 340 kΩ, 1% or better for the upper resistor
Ra. Then the value of the bottom resistor Rb in
kΩ is given as:
Layout Considerations
204
Proper layout and placement of external
components is critical to optimal functioning of
the converter and for minimizing radiated and
conducted noise.
Rb =
kΩ
VOUT − 0.6
Where VOUT is the output voltage. Rb should
also be a 1% or better resistor.
Follow
these
layout
guidelines
as
demonstrated on the EN5322 customer eval
boards:
Input and Output Capacitor Selection
Low ESR MLC capacitors with X5R or X7R or
equivalent dielectric should be used for input
and output capacitors. Y5V or equivalent
dielectrics lose too much capacitance with
frequency, DC bias, and temperature.
Therefore, they are not suitable for switch-
mode DC-DC converter filtering, and must be
avoided.
1. Input and output capacitors should be
placed on the same side of the PCB as
the EN5322 and immediately adjacent to
their respective pins on the package. To
minimize parasitic inductances, the traces
for making these connections should be
as short and wide as possible.
2. A row of vias connecting these capacitors’
ground pads to the PCB GND plane
should be placed along the edge of the
capacitor ground copper closest to the
positive capacitor pads. These vias
should start as close to the device as
possible and continue underneath the
capacitors.
A 10 μF, 10 V, 0805 MLC capacitor is needed
on PVIN for all applications. A 1 μF, 10 V, 0402
MLC capacitor on AVIN is needed for high
frequency bypass to ensure clean chip supply
for optimal performance.
A 47 μF, 6.3 V, 1206 MLC capacitor is
recommended on the output for most
applications. The output ripple can be reduced
by approximately 50% by using 2 x 22 μF,
6.3V, 0805 MLC capacitors rather than 1 x 47
μF.
3. Avoid adding a test pin or test pad for
NC(SW) pins on the PCB. Doing so can
compromise the GND plane and result in
degradation of the performance.
4. There should be as many vias as possible
connecting the thermal pad under the
device to the PCB GND plane for best
thermal performance. Ideally, the vias
should have a drill diameter of 0.33 mm
(10 mils) with at least 1 oz copper plating
in the barrel.
Table 2. Recommended input and output capacitors
Description
10μF, 10V,
X5R, 10%,
0805
Mfg.
Taiyo Yuden
Murata
P/N
LMK212BJ106KG
GRM21BR71A106KE51L
ECJ-2FB1A106K
CIN
Panasonic
5. Keep the input and output current loops
separate from each other as much as
possible. Keep sensitive signals on the
PCB away from the power supply circuit.
6. Connect the VSENSE trace to the last
local output capacitor. Make sure the
trace inductance between the output
capacitors and the sensing point is
minimized. The VSENSE trace should
also be kept away from noisy signals that
can contaminate it.
Taiyo Yuden
Murata
Kemet
JMK316BJ476ML
GRM31CR60J476ME19L
C1206C476M9PACTU
47μF, 6.3V,
X5R, 20%,
1206
COUT
POK Pull Up Resistor Selection
POK can be pulled up through a resistor to any
voltage source as high as VIN. The simplest
way is to connect POK to the power input of
the converter through a resistor. A 100 kΩ pull
up resistor is typically recommended for most
©Enpirion 2008 all rights reserved, E&OE
12
www.enpirion.com
03454
4/24/2009
Rev:A
ENPIRION [ ENPIRION, INC. ]
