EM6603
Table of Contents
Table of Figures
Figure 1.Architecture
1
OPERATING MODES
STANDBY MODE
SLEEP MODE
5
5
5
1
1
1.1
1.2
Figure 2.Pin Configuration
Figure 3.Typical Configuration
Figure 4.Mode Transition diagram
Figure 5.System reset generation
Figure 6.Port A
4
5
2
POWER SUPPLY
5
6
10
11
13
14
16
19
22
23
25
34
34
35
35
3
RESET
6
6
6
7
7
7
Figure 7.Port B
3.1
3.2
3.3
3.4
3.5
OSCILLATION DETECTION CIRCUIT
RESET PIN
Figure 8.Port C
Figure 9.Port D
INPUT PORT (PA0..PA3) RESET
WATCHDOG TIMER RESET
CPU STATE AFTER RESET
Figure 10.Timer / Event Counter
Figure 11.Interrupt Request generation
Figure 12.Serial write buffer
Figure 13.Automatic Serial Write Buffer transmission
Figure 14.Interactive Serial Write Buffer transmission
Figure 15. EM6603 PAD Location Diagram
4
OSCILLATOR
8
4.1
PRESCALER
8
Figure 16. Dimensions of PDIP24 Pack. - Pack. type “A”
Figure 17. Dimensions of TSSOP24 Pack. - Pack. type “F”
Figure 18. Dimensions of SOP24 Pack. SOIC – Pack. type “B”
5
WATCHDOG TIMER
8
6
INPUT AND OUTPUT PORTS
PORTA
9
9
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Table of Tables
PORTA REGISTERS
PORTB
10
11
11
12
12
14
14
Table 1. Pin Description
4
5
Table 2.StandBy and Sleep Activities
PORTB REGISTERS
PORTC
Table 3. PortA Inputs RESET options (metal Hardware option)
Table 4. Watchdog-Timer Option (software option)
Table 5. Initial Value After RESET
7
7
PORTC REGISTERS
PORTD
7
Table 6.Prescaler interrupt source
8
Table 7. Prescaler control register - PRESC
Table 8.Watchdog register - WD
8
PORTD REGISTERS
8
7
BUZZER
15
Table 9.Input / Output Ports Overview
Table 10.Option register - Option
9
7.1
BUZZER REGISTER
15
Table 11.PortA input status register - PortA
Table 12.PortA Interrupt request register - IRQpA
Table 13.PortA interrupt mask register - MportA
Table 14.PortB input status register - PortB
Table 15.PortB Input/Output control register - CIOportB
Table 16.Ports A&C Interrupt Request
Table 17.PortC input/output register - PortC
Table 18.PortC Interrupt request register - IRQpC
Table 19.PortC interrupt mask register - MportC
Table 20.PortD Input/Output register - PortD
Table 21.Ports control register - CPIOB
Table 22.Buzzer frequency selection
8
TIMER/EVENT COUNTER
16
8.1
TIMER/COUNTER REGISTERS
17
9
INTERRUPT CONTROLLER
18
9.1
INTERRUPT CONTROL REGISTERS
18
10
SUPPLY VOLTAGE LEVEL DETECTOR (SVLD)
20
10.1
SVLD REGISTER
20
11
SERIAL (OUTPUT) WRITE BUFFER – SWB
SWB AUTOMATIC SEND MODE
21
23
25
11.1
11.2
SWB INTERACTIVE SEND MODE
Table 23.Buzzer control register - BEEP
Table 24.Timer Clock Selection
12
13
14
15
15
STROBE / RESET OUTPUT
26
Table 25.Timer control register - TimCtr
TEST AT EM - ACTIVE SUPPLY CURRENT TEST 26
METAL MASK OPTIONS
27
28
28
Table 28.PA3 counter input selection register - PA3cnt
Table 29.PA3 counter input selection
Table 30.Main Interrupt request register - IntRq (Read Only)*
Table 31.register - CIRQD
PERIPHERAL MEMORY MAP
Table 32. SVLD level selection
Table 33.SVLD control register - SVLD
Table 34.SWB clock selection
16
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
30
30
30
30
30
31
16.1
16.2
16.3
16.4
16.5
16.6
Table 35.SWB clock selection register - ClkSWB
Table 36.PortD status
STANDARD OPERATING CONDITIONS
HANDLING PROCEDURES
Table 37.SWB buffer register - SWbuff
Table 38.SWB Low size register - LowSWB
Table 39.SWB High size register - HighSWB
Table 40 Input/Output Ports
DC CHARACTERISTICS - POWER SUPPLY PINS
DC CHARACTERISTICS - INPUT/OUTPUT PINS
DC CHARACTERISTICS - SUPPLY VOLTAGE DETECTOR
LEVELS
Table 41 PortA RESET option
32
33
33
Table 42 SVLD levels
16.7
16.8
OSCILLATOR
INPUT TIMING CHARACTERISTICS
17
PAD LOCATION DIAGRAM
34
18
PACKAGE AND ORDERING INFORMATION
ORDERING INFORMATION
34
36
36
36
18.1
18.2
18.3
PACKAGE MARKING
CUSTOMER MARKING
19
SPECIFICATION CHANGE
37
03/02 REV. G/439
3
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