EM78P510N
8-Bit Microcontrollers
Status
Affected
Binary Instruction
Hex
Mnemonic
Operation
[Top of Stack] → PC,
Enable Interrupt
0 0000 0001 0011
0013
RETI
None
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0 0101 01rr rrrr
0 0101 10rr rrrr
0 0101 11rr rrrr
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
MOV R,A
CLRA
A → R
None
0 → A
Z
CLR R
0 → R
Z
SUB A,R
SUB R,A
DECA R
DEC R
R-A → A
Z, C, DC
R-A → R
R-1→A
Z, C, DC
Z
R-1 →R
Z
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
A ∨ R →A
A ∨ R → R
A & R → A
A & R →R
A ♁ R →A
A ♁ R → R
A + R → A
A + R → R
R → A
Z
Z
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
R → R
Z
Z
/R → A
/R → R
Z
INCA R
INC R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
Z
Z
DJZA R
DJZ R
None
None
R(n) → A(n-1),
R(0) → C, C → A(7)
0 0110 00rr rrrr
0 0110 01rr rrrr
0 0110 10rr rrrr
0 0110 11rr rrrr
0 0111 00rr rrrr
06rr
06rr
06rr
06rr
07rr
RRCA R
RRC R
C
C
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
RLCA R
RLC R
C
R(n) → R(n+1),
R(7) → C, C → R(0)
C
R(0-3) → A(4-7),
R(4-7) → A(0-3)
SWAPA R
None
0 0111 01rr rrrr
0 0111 10rr rrrr
07rr
07rr
SWAP R
JZA R
R(0-3) ↔ R(4-7)
None
None
R+1 → A, skip if zero
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
• 93
ELAN [ ELAN MICROELECTRONICS CORP ]
