EM78P510N
8-Bit Microcontrollers
6.16 Instruction Set
Each instruction in the Instruction Set is a 13-bit word divided into an OP code and one
or more operand. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅). In this case, the
execution takes two instruction cycles.
The following are executed within two instruction cycles; "LJMP", "LCALL", or
conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") instructions which were
tested to be true. Instructions written to the program counter are also executed within
two instruction cycles.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction
can operate on the I/O register.
Convention:
r = Register designator that specifies which one of the registers (including operation and general purpose
registers) is to be utilized by the instruction.
Bits 6 and 7 in R4 determine the selected register bank.
b = Bit field designator that selects the value for the bit located in the register R and which affects the
operation.
k = 8 or 10-bit constant or literal value
Status
Binary Instruction
Hex
Mnemonic
Operation
No Operation
Affected
None
C
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0011
0 0000 0000 0100
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
0000
0001
0003
0004
0010
0011
0012
NOP
DAA
SLEP
WDTC
ENI
Decimal Adjust A
0 → WDT, Stop oscillator
0 → WDT
T, P
T, P
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
None
None
None
DISI
RET
92 •
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
