EM78P458/459
OTP ROM
4.9 Timer
1. Overview
Timer1 (TMR1) and Timer2 (TMR2) (TMRX) are 10-bit clock counters with programmable prescalers,
respectively. They are designed for the PWM module as baud rate clock generators. TMRX can be
read, written, and cleared at any reset conditions.
2. Function description
Fig. 15 shows TMRX block diagram. Each signal and block are described as follows:
Fosc
1:2
To PWM1IF
1:8
1:32
1:64
MUX
reset
Period
TMR1X
Match
Comparator
T1P0 T1P1
T1EN
PRD1
PRD2
Data Bus
Data Bus
T2P0 T2P1 T2EN
Comparator
reset
Period
Match
Fosc
1:2
TMR2X
1:8
1:32
1:64
MUX
To PWM2IF
*TMR1X = TMR1H + TMR1L;
*TMR2X = TMR2H +TMR2L
Fig. 15 TMRX Block Diagram
Fosc: Input clock.
Prescaler ( T1P0 and T1P1/T2P1 and T2P0 ): Options of 1:2, 1:8, 1:32, and 1:64 are defined by
TMRX. It is cleared when any type of reset occurs.
TMR1X and TMR2X (TMR1H/TWR1L and TMR2H/TMR2L ):
Timer
X
register; TMRX is
increased until it matches with PRDX, and then is reset to 0. TMRX cannot be read.
PRDX ( PRD1 and PRD2 ): PWM period register.
ComparatorX ( Comparator 1 and Comparator 2 ): To reset TMRX while a match occurs and the
TMRXIF flag is set at the same time.
This specification is subject to change without prior notice.
40
06.25.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
