EM78P458/459
OTP ROM
following events occur on the next increment cycle:
• TMRX is cleared.
• The PWMX pin is set to 1.
• The PWM duty cycle is latched from DT1/DT2 to DTL1/DTL2.
< Note > The PWM output will not be set, if the duty cycle is 0;
• The PWMXIF pin is set to 1.
The following formula describes how to calculate the PWM period:
PERIOD = (PRDX + 1) * 4 * (1/Fosc) * (TMRX prescale value )
4. PWM Duty Cycle ( DTX: DT1H/ DT1L and DT2H/ DT2L; DTL: DL1H/DL1L and
DL2H/DL2L )
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to DLX while
TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX can be loaded at any
time. However, it cannot be latched into DTL until the current value of DLX is equal to TMRX.
The following formula describes how to calculate the PWM duty cycle:
Duty Cycle = (DTX) * (1/Fosc) * (TMRX prescale value )
5. Comparator X
To change the output status while the match occurs, the TMRXIF flag will be set at the same time.
6. PWM Programming Procedures/Steps
(1) Load PRDX with the PWM period..
(2) Load DTX with the PWM Duty Cycle.
(3) Enable interrupt function by writing IOCF0, if required.
(4) Set PWMX pin to be output by writing a desired value to IOC51.
(5) Load a desired value to IOC51 with TMRX prescaler value and enable both PWMX and TMRX.
This specification is subject to change without prior notice.
39
06.25.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
