EM78P458/459
OTP ROM
latch
To PWM1IF
DL1H + DL1L
Comparator
DT1H
+
DT1L
Fosc
Duty Cycle
Match
1:2
PWM1
1:8
MUX
1:32
1:64
R
S
Q
TMR1H + TMR1L
reset
IOC51
Comparator
T1P0 T1P1 T1EN
Period
Match
PRD1
Data Bus
Data Bus
latch
To PWM2IF
DL2H + DL2L
DT2H
+
DT2L
Duty Cycle
Match
T2P0 T2P1 T2EN
Comparator
PWM2
Fosc
R
S
Q
TMR2H + TMR2L
1:2
reset
1:8
MUX
1:32
1:64
IOC51
Comparator
Period
Match
PRD2
Fig. 13 The Functional Block Diagram of the Dual PWMs
Period
Duty Cycle
PRD1 = TMR1
DT1 = TMR1
Fig. 14 The Output Timing of the PWM
2. Increment Timer Counter ( TMRX: TMR1H/TWR1L or TMR2H/TWR2L )
TMRX are ten-bit clock counters with programmable prescalers. They are designed for the PWM
module as baud rate clock generators. TMRX can be read, written, and cleared at any reset
conditions. If employed, they can be turned down for power saving by setting T1EN bit
[PWMCON<4>] or T2EN bit [PWMCON<5>] to 0.
3. PWM Period ( PRDX : PRD1 or PRD2 )
The PWM period is defined by writing to the PRDX register. When TMRX is equal to PRDX, the
This specification is subject to change without prior notice.
38
06.25.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
