EM78P458/459
OTP ROM
7
-
6
5
4
3
2
EXIF
1
ICIF
0
TCIF
CMPIF
PWM2IF
PWM1IF
ADIF
“1” means interrupt request, and “0” means no interrupt occurs.
• Bit 7 Unemployed, read as ‘0’;
• Bit 6 (CMPIF) High-compared interrupt flag. Set when a change occurs in the output of Comparator,
reset by software.
• Bit 5 (PWM2IF) PWM2 (Pulse Width Modulation) interrupt flag. Set when a selected period is
reached, reset by software.
• Bit 4 (PWM1IF) PWM1 (Pulse Width Modulation) interrupt flag. Set when a selected period is
reached, reset by software.
• Bit 3 (ADIF) Interrupt flag for analog to digital conversion. Set when AD conversion is completed,
reset by software.
• Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.
• Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes, reset by
software.
• Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software.
• RF can be cleared by instruction but cannot be set.
• IOCF0 is the interrupt mask register.
• Note that to read RF will result to "logic AND" of RF and IOCF0.
15. R10 ~ R3F
• All of these are 8-bit general-purpose registers.
4.2 Special Purpose Registers
1. A (Accumulator)
• Internal data transfer, or instruction operand holding
• It can not be addressed.
2. CONT (Control Register)
7
6
INT
5
TS
4
TE
3
PAB
2
1
0
INTE
PSR2
PSR1
PSR0
• Bit 7 (INTE) INT signal edge
0: interrupt occurs at the rising edge on the INT pin
1: interrupt occurs at the falling edge on the INT pin
• Bit 6 (INT) Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by the ENI/RETI instructions
This specification is subject to change without prior notice.
13
06.25.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
