EM78P458/459
OTP ROM
Address
PAGE registers
IOC PAGE registers
IOC PAGE registers
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
R0 (IAR)
Reserve
Reserve
Reserve
Reserve
R1 (TCC)
R2 (PC)
Reserve
Reserve
R3 (Status)
Reserve
Reserve
R4 RSR)
Reserve
Reserve
R5 (Port5)
IOC50 (I/O Port Control Register)
IOC60 (I/O Port Control Register)
Reserve
IOC51 (PWMCON)
IOC61 (DT1L)
IOC71 (DT1H)
IOC81 (PRD1)
IOC91 (DT2L)
IOCA1 (DT2H)
R6 (Port6)
R7 General Registers
R8 General Registers
R9 (ADCON)
RA (ADDATA)
RB General Registers
Reserve
IOC90 (GCON)
IOCA0 (AD-CMPCON)
IOCB0 (Pull-down Control Register) IOCB1 (PRD2)
IOCC0 (Open-drain Control Register) IOCC1 (DL1L)
IOCD0 (Pull-high Control Register) IOCD1 (DL1H)
RC General Registers
(Only two bits)
RD General Registers
RE General Registers
IOCE0 (WDT Control Register)
IOCF0 (Interrupt Mask Register)
IOCE1 (DL2L)
IOCF1 (DL2H)
(Only two bits)
0F
10
RF (Interrupt status)
General Registers
1F
20
Bank 0
Bank 1
3F
Fig. 4 Data Memory Configuration
This specification is subject to change without prior notice.
10
06.25.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
