EM78P350N
8-Bit Microprocessor with OTP ROM
Bit 2 ~ Bit 0 (T1P2 ~ T1P0): TMR1 clock prescale option bits
T1P2
T1P1
T1P0
Prescale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2 (default)
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.1.16 Bank 1 R6 (PWM Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T2EN
T2P2
T2P1
T2P0
T3EN
T3P2
T3P1
T3P0
Bit 7 (T2EN):
TMR2 enable bit
0 = TMR2 is off (default value)
1 = TMR2 is on
Bit 6 ~ Bit 4 (T2P2 ~ T2P0): TMR2 clock prescale option bits
T2P2
T2P1
T2P0
Prescale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2 (default)
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 3 (T3EN):
TMR3 enable bit
0 = TMR3 is off (default value)
1 = TMR3 is on
Bit 2 ~ Bit 0 (T3P2 ~ T3P0): TMR3 clock prescale option bits
T3P2
T3P1
T3P0
Prescale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2 (default)
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Product Specification (V 1.0) 09.14.2006
(This specification is subject to change without further notice)
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