EM78P350N
8-Bit Microprocessor with OTP ROM
6.4.1 Usage of Port 6 Input Change Wake-up/Interrupt Function
(1) Wake-up
(a) Before Sleep
(2) Wake-up and Interrupt
(a) Before Sleep
1. Disable WDT
1. Disable WDT
2. Read I/O Port 6 (MOV R6,R6)
3. Execute "ENI" or "DISI"
2. Read I/O Port 6 (MOV R6,R6)
3. Execute "ENI" or "DISI"
4. Enable wake-up bit (Set RE
ICWE =1)
4. Enable wake-up bit (Set RE ICWE =1)
5. Execute "SLEP" instruction
(b) After wake-up
5. Enable interrupt (Set IOCF ICIE =1)
6. Execute "SLEP" instruction
(b) After wake-up
→ Next instruction
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
(3) Interrupt
(a) Before Port 6 pin change
1. Read I/O Port 6 (MOV R6,R6)
2. Execute "ENI" or "DISI"
3. Enable interrupt (Set IOCF ICIE =1)
(b) After Port 6 pin changed (interrupt)
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
6.5 Serial Peripheral Interface Mode
6.5.1 Overview and Features
Overview:
Figures 6-7, 6-8, and 6-9 shows how the EM78P350N communicates with other
devices through SPI module. If the EM78P350N is a master controller, it sends clock
through the SCK pin. A couple of 8-bit data are transmitted and received at the same
time. However, if EM78P350N is defined as a slave, its SCK pin could be programmed
as an input pin. Data will continue to be shifted based on both the clock rate and the
selected edge. The SPIS Bit 7 (DORD) can also be set to determine the SPI
transmission order, SPIC Bit 3 (SDOC) to control SDO pin after serial data output
status and SPIS Bit 6 (TD1), Bit 5 (TD0) determines the SDO status output delay times.
Features:
Operation in either Master mode or Slave mode
Three-wire or four-wire full duplex synchronous communication
Programmable baud rates of communication,
Programming the clock polarity, (RD Bit 7)
Interrupt flag available for the read buffer full,
Product Specification (V 1.0) 09.14.2006
(This specification is subject to change without further notice)
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