EM78P350N
8-Bit Microprocessor with OTP ROM
Bit 3 (SOUTC): Sout output status control bit:
0 = After the Serial data output, the Sout remains high
1 = After the Serial data output, the Sout remains low
Bit 2~Bit 0 (SBRS): SPI Baud Rate Select bits
Refer to the SPI baud rate table under the “SPI” section on the subsequent pages.
6.1.12 RE (WUCR: Wake-up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EM78P350N
“0”
“0”
“0”
LVDIF* ADWE CMPWE ICWE PWMWE
ICE350N
Simulator
C3
C2
C1
C0
ADWE CMPWE ICWE PWMWE
*There is no LVD function in the ICE350N simulator.
Bit 7 ~ Bit 5: [EM78P350N]: Unimplemented, read as ‘0’.
Bit 4 (LVDIF) (only for EM78P350N) : Low voltage Detector interrupt flag.
LVDEN
<RE,3>
LVD1,LVD0
<RE,1,0>
LVD Voltage Interrupt Level
LVDIF
1
1
1
11
10
01
2.2V
3.3V
4.0V
1*
1*
1*
1
0
00
4.5V
NA
1*
0
XX
* If Vdd has crossover at LVD voltage interrupt level as Vdd changes, LVDIF =1.
[With Simulator (C3~C0)]: are IRC calibration bits in IRC oscillator mode. In IRC
oscillator mode of ICE350N simulator, these are the IRC calibration bits of IRC
oscillator mode.
C3
C2
C1
C0
Frequency (MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
(1-36%) x F
(1-31.5%) x F
(1-27%) x F
(1-22.5%) x F
(1-18%) x F
(1-13.5%) x F
(1-9%) x F
(1-4.5%) x F
F (default)
(1+4.5%) x F
(1+9%) x F
(1+135%) x F
(1+18%) x F
(1+22.5%) x F
(1+27%) x F
(1+31.5%) x F
Note: 1. Frequency values shown are theoretical and taken from an instance of a high frequency mode.
Hence, they are shown for reference only. Definite values depend on the actual process.
2. Similar way of calculation is also applicable for low frequency mode.
12 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
