EM78P350N
8-Bit Microprocessor with OTP ROM
6.1.3.1 Data Memory Configuration
Register
Bank 0
Register
Bank 1
Register
Bank 2
Register
Bank 3
Control
Register
Address
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
R1 (TCC Buffer)
R2 (PC)
R3 (STATUS)
R4 (7, 6)
(0, 1)
R4 (7, 6)
(1, 0)
R4 (7, 6)
(1, 1)
R4 (RSR, Bank Select)
R5 (Port 5 I/O data)
R6 (Port 6 I/O data)
R7 (Port 7 I/O data)
R8 (Port 8 I/O data)
R5 (PWM Control
Register #1)
R5 (Pull Low Control 1)
R6 (Pull Low Control 2)
R7 (Pull Low Control 3)
R8 (Pull Low Control 4)
R9 (Pull High Control 1)
RA (Pull High Control 2)
RB (Pull High Control 3)
RC (Pull High Control 4)
IOC5 (Port 5 I/O control)
IOC6 (Port 6 I/O control)
IOC7 (Port 7 I/O control)
IOC8 (Port 8 I/O control)
Reserved
R6 (PWM Control
Register #2)
R6 (Buzzer output
Control Register)
R7 (System control
Register)
R7 (PWM timer/counter
Control register)
R8 (PRD1H: PWM1
period)
R8 (TADC input
select register)
R9 (Timer 4 control
register)
R9 (PRD2H: PWM2
period)
R9 (ADC control
register)
IOC9 (Timer 4 control
register)
RA (PRD3H: PWM3
period)
RA (ADC offset
IOCA (Comparator
Control Register )
RA (SPI read buffer)
RB (SPI write buffer)
RC (SPI status buffer)
RD (SPI control buffer )
calibration register)
RB (PRDL: PWM
Period cycle)
RB (ADDATA ADC
Data Bit11~Bit4)
Reserved
Reserved
Reserved
RC (DT1L: PWM1
Duty cycle)
RC (ADDATA1H ADC
Data Bit 11~Bit 8)
RD (DT2L: PWM2
Duty cycle)
RD (TIMER1H: PWM1
timer)
RD (ADATA1L ADC
Data Bit 7~Bit 0)
RE (Wake-up control
register)
RE (DT3L: PWM3 Duty
cycle)
RE (TIMER2H: PWM2
timer)
IOCE (WDT control
register)
RE (LVDC : LVD
Control)
RF (DTH: PWM
Duty cycle)
RF (TIMER3H: PWM3
timer)
RF (Interrupt flag)
RF (TMRL: PWM timer) IOCF (Interrupt Mask 1)
10
:
16-Byte Common Register
1F
20
:
3F
Bank 2
32 x 8
Bank 3
32 x 8
Bank 0
32 x 8
Bank 1
32 x 8
8 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
