EM78P350N
8-Bit Microprocessor with OTP ROM
6.1.17 Bank1 R7 (PWM Timer/Counter Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
“0”
“0”
“0”
“0”
T2TS
T2TE
T1TS
T1TE
Bits 7~4: Unimplemented, read as ‘0’
Bit 3 (T2TS): Timer 2 / Counter 2 signal source
0 = internal instruction cycle clock. If P77 is used as I/O pin, T2TS must
be 0
1 = transition on the CNTR2 pin
Bit 2 (T2TE): Timer 2 / Counter 2 signal edge
0 = increment if a transition from low to high takes place on the CNTR2
pin
1 = increment if a transition from high to low takes place on the CNTR2
pin
Bit 1 (T1TS): Timer 1 / Counter 1 signal source
0 = internal instruction cycle clock. If P76 is used as I/O pin, T1TS must
be 0
1 = transition on the CNTR1 pin
Bit 0 (T1TE): Timer 1 / Counter 1 signal edge
0 = increment if a transition from low to high takes place on the CNTR1
pin
1 = increment if a transition from high to low takes place on the CNTR1
pin
6.1.18 Bank1 R8 (PRD1H: Most Significant Byte (Bit 9 ~ Bit 2) of
PWM1 Time Period)
The content of Bank 1 R8 is the time period (time base) of PWM1. The frequency of
PWM1 is the reverse of the period.
6.1.19 Bank1 R9 (PRD2H: Most Significant Byte (Bit 9 ~ Bit 2) of
PWM2 Time Period)
The content of Bank 1 R9 is the time period (time base) of PWM2. The frequency of
PWM2 is the reverse of the period.
6.1.20 Bank1 RA (PRD3H: Most Significant Byte (Bit 9 ~ Bit 2) of
PWM3 Time Period)
The content of Bank 1 RA is the time period (time base) of PWM3. The frequency of
PWM3 is the reverse of the period.
16 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
