EM78P312N
8-Bit Microcontroller
Status
Affected
Binary Instruction
Hex Mnemonic
Operation
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000
0000
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
01rr rrrr
1000 0000
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr
0080 CLRA
MOV
R,
A
A → R
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
0 → A
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
CLR
SUB
SUB
DECA
DEC
OR
R
0 → R
R-A → A
R-A → R
R-1 → A
R-1 → R
A ∨ R → A
A ∨ R → R
A & R → A
A & R → R
A ⊕ R → A
A ⊕ R → R
A + R → A
A + R → R
R → A
R → R
/R → A
A,
R,
R
R
A
R
A,
R,
A,
R,
A,
R,
A,
R,
A,
R,
R
R
A
R
A
R
A
R
A
R
R
OR
AND
AND
XOR
XOR
ADD
ADD
MOV
MOV
COMA
COM
INCA
INC
R
R
R
R
/R → R
R+1 → A
R+1 → R
DJZA
DJZ
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → (C), C → (R(0)
R(0-3) → ( A(4-7),
R(4-7) → ( A(0-3)
R(0-3) → ( R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0→ ( R(b)
None
None
R
0
0
0
0
0
0110
0110
0110
0110
0111
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
06rr
06rr
06rr
06rr
07rr
RRCA
RRC
R
R
R
R
R
C
C
RLCA
RLC
C
C
SWAPA
None
0
0
0
0
0
0
0
0111
0111
0111
100b
101b
110b
111b
01rr rrrr
10rr rrrr
11rr rrrr
bbrr rrrr
bbrr rrrr
bbrr rrrr
bbrr rrrr
07rr
07rr
07rr
0xxx BC
0xxx BS
0xxx JBC
0xxx JBS
SWAP
JZA
JZ
R
R
R
R,
R,
R,
R,
None
None
None
None
None
None
None
b
b
b
b
1→ ( R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP],
(Page, k) → (PC)
(Page, k) → (PC)
k → A
A v k → A
A & k → A
A ⊕ k → A
1
00kk
kkkk kkkk
1kkk CALL
k
None
1
1
1
1
1
01kk
1000
1001
1010
1011
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
1kkk JMP
18kk MOV
19kk OR
1Akk AND
1Bkk XOR
k
None
None
Z
Z
Z
A,
A,
A,
A,
k
k
k
k
k → A, [Top of Stack] →
PC
1
1100
kkkk kkkk
1Ckk RETL
k
None
1
1
1
1
1101
1111
1110
1110
kkkk kkkk
kkkk kkkk
1000 kkkk
1001 kkkk
1Dkk SUB
1Fkk ADD
1E8k PAGE
1E9k BANK
A,
A,
k
k
k
k-A → A
k+A → A
K->R5(6:4)
K->R4(7:6)
Z,C,DC
Z,C,DC
None
k
None
Note: 1 This instruction is applicable to IOC6~IOCA, IMR1, IMR2 only.
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
• 57
ELAN [ ELAN MICROELECTRONICS CORP ]
