EM78P312N
8-Bit Microcontroller
5.19 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅). In this case, the
execution takes two instruction cycles.
In case the instruction cycle specification is not suitable for certain applications, try to
modify the instruction as follows:
(A) Change one instruction cycle to consist of 4 oscillator periods.
(B) The following commands are executed within two instruction cycles; "JMP",
"CALL", "RET", "RETL", "RETI", including the conditional skip ("JBS", "JBC", "JZ",
"JZA", "DJZ", "DJZA") instructions. In addition, instructions that are written to the
program counter are executed within two instruction cycles.
Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle
consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high.
Note that once the 4 oscillator periods within one instruction cycle is selected as in
Case (A), the internal clock source to TCC should be CLK=Fosc/4, not Fosc/2.
Furthermore, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
Convention:
R = Register designator that specifies which one of the registers (including operation and general purpose
registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the register R and which affects the
operation.
k = 8 or 10-bit constant or literal value
Status
Affected
Binary Instruction
Hex Mnemonic
Operation
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop
oscillator
0
0
0
0000
0000
0000
0000 0000
0000 0001
0000 0010
0000 NOP
0001 DAA
0002 CONTW
None
C
None
0
0000
0000 0011
0003 SLEP
0004 WDTC
T, P
0
0
0
0
0
0000
0000
0000
0000
0000
0000 0100
0000 rrrr
0001 0000
0001 0001
0001 0010
0 → WDT
A → IOCR
T, P
000r IOW
0010 ENI
0011 DISI
0012 RET
R
None 1
None
None
None
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
CONT → A
0
0000
0001 0011
0013 RETI
None
0
0
0000
0000
0001 0100
0001 rrrr
0014 CONTR
001r IOR
None
R
IOCR → A
None 1
56 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
