EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 6 ~ Bit 4 (HTS2 ~ HTS0): High-time scale bits:
HTS2
HTS1
HTS0
High-time rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 3 (LTSE):
Low-time scale enable bit.
0 = scale disable bit, Low-time rate is 1:1
1 = scale enable bit, Low-time rate is set as Bit 2~Bit 0.
Bit 2 ~ Bit 0 (LTS2 ~ LTS0): Low-time scale bits:
LTS2
LTS1
LTS0
Low-time rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.2.19 IOCC1 (TCC Prescaler Counter)
TCC prescaler counter can be read and written:
TCC
Rate
PST2 PST1 PST0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1:2
1:4
-
-
V
V
V
V
V
V
V
-
-
-
-
-
V
V
V
V
V
V
1:8
-
-
-
-
V
V
V
V
V
1:16
1:32
1:64
1:128
1:256
-
-
-
V
V
V
V
-
-
V
V
V
-
V
V
V
V = valid value
The TCC prescaler counter is assigned to TCC (R1).
The contents of the IOCC1 register are cleared when one of the following occurs:
ꢀ
ꢀ
ꢀ
ꢀ
a value is written to TCC register
a value is written to TCC prescaler bits (Bit 3,2,1,0 of CONT)
power on reset, /RESET
WDT time out reset
Product Specification (V1.0) 06.16.2005
• 27
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
