EM78P258N
8-Bit Microprocessor with OTP ROM
6.2.5 IOC90 (TCCB and TCCC Control Register)
7
6
5
4
3
2
1
0
TCCBHE TCCBEN
-
-
–
TCCCEN
-
-
Bit 7 (TCCBHE): Control bit is used to enable the most significant byte of counter
1 = Enable the most significant byte of TCCBH
TCCB is a 16-bit counter
0 = Disable the most significant byte of TCCBH (default value)
TCCB is an 8-bit counter
Bit 6 (TCCBEN): TCCB enable bit
0 = disable TCCB
1 = enable TCCB as a counter
Bit 5 & Bit 4:
Bit 3:
Not used, fixed to “0”.
Not used.
Bit 2 (TCCCEN): TCCC enable bit
0 = disable TCCC
1 = enable TCCC as a counter
Not used, fixed to “0”.
Bit 1 & Bit 0:
6.2.6 IOCA0 (IR and TCCC Scale Control Register)
7
6
5
4
3
2
1
0
TCCCSE TCCCS2 TCCCS1 TCCCS0
IRE
HF
LGP
IROUTE
Bit 7 (TCCCSE): Scale enable bit for TCCC
An 8-bit counter is provided as scale for TCCC and IR-Mode. When
in IR-Mode, TCCC counter scale uses the low-time segments of the
pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in
Section 6.8.2, Function Description).
0 = scale disable bit, TCCC rate is 1:1
1 = scale enable bit, TCCC rate is set as Bit 6 ~ Bit 4
Product Specification (V1.0) 06.16.2005
• 17
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
