EM78P258N
8-Bit Microprocessor with OTP ROM
6.2 Special Purpose Registers
6.2.1 A (Accumulator)
Internal data transfer, or instruction operand holding. It cannot be addressed.
6.2.2 CONT (Control Register)
7
6
5
4
3
2
1
0
INTE
INT
TS
TE
PSTE
PST2
PST1
PST0
NOTE
■ The CONT register is both readable and writable.
■ Bit 6 is read only.
Bit 7 (INTE): INT signal edge
0 = interrupt occurs at the rising edge on the INT pin
1 = interrupt occurs at the falling edge on the INT pin
Bit 6 (INT): Interrupt enable flag
0 = masked by DISI or hardware interrupt
1 = enabled by the ENI/RETI instructions
This bit is readable only.
Bit 5 (TS):
Bit 4 (TE):
TCC signal source
0 = internal instruction cycle clock. P54 is bi-directional I/O pin.
1 = transition on the TCC pin
TCC signal edge
0 = increment if the transition from low to high takes place on the TCC
pin
1 = increment if the transition from high to low takes place on the TCC
pin.
Bit 3 (PSTE): Prescaler enable bit for TCC
0 = prescaler disable bit. TCC rate is 1:1.
1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.
Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits
PST2 PST1 PST0 TCC Rate
0
0
0
1:2
1:4
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1:8
1:16
1:32
1:64
1:128
1:256
Product Specification (V1.0) 06.16.2005
• 15
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
