EM78P258N
8-Bit Microprocessor with OTP ROM
NOTE
Tcc timeout period [1/Fosc x prescaler x 256(Tcc cnt) x 1(CLK=2)]
Tcc timeout period [1/Fosc x prescaler x 256(Tcc cnt) x 2(CLK=4)]
6.2.3 IOC50 ~ IOC70 (I/O Port Control Register)
ꢀ
"1" puts the relative I/O pin into high impedance, while "0" defines the relative I/O
pin as output.
ꢀ
ꢀ
ꢀ
ꢀ
Only the lower 6 bits of IOC50 can be defined.
Only the bit1, 2, 6 and, 7 of IOC60 can be defined.
Only the lower 1 bits of IOC70 can be defined, the others bits are not available.
IOC50, IOC60, and IOC70 registers are all readable and writable
6.2.4 IOC80 (TCCA Control Register)
7
6
5
4
3
2
1
0
–
–
-
-
-
TCCAEN TCCATS TCCATE
NOTE
■ Bit4 ~ 0 of IOC80 register is both readable and writable.
■ Bit5 of IOC80 register is readable only.
Bit 7 ~ Bit 5:
Bit 4 & Bit 3:
Not used
Not used, fixed to “0”.
Bit 2 (TCCAEN): TCCA enable bit
0 = disable TCCA
1 = enable TCCA as a counter
TCCA signal source
Bit 1 (TCCATS):
Bit 0 (TCCATE):
0 =: internal instruction cycle clock. P61 is a bi-directional I/O pin.
1 = transit through the TCCA pin
TCCA signal edge
0 = increment if transition from low to high takes place on the
TCCA pin
1 = increment if transition from high to low takes place on the
TCCA pin
16 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
