EM78P257
OTP ROM
• Bit 0(PWM) Pulse Width Modulation. When PWM = 1 and LGP = 0, the LSB Counter and MSB
Counter are disabled, a continuous pulse train is generated, and the output signal is actually a PWM
waveform format of PWM.
13. RE (Mouse Control Register)
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
MOUSEN
• Bit 7 (MOUSEN) Mouse application Enable bit.
0: Disable MOUSEN. TCCA, TCCB and TCCC are increment counters.
1: Enable MOUSEN. TCCA, TCCBL and TCCC work as up/down counters. The other pin
assignment refers to IOC80 and IOC90.
• Bit 6~Bit 0 Not used.
14. RF (Interrupt Status Register)
7
6
5
4
3
-
2
1
0
CMP4IF
CMP3IF
CMP2IF
CMP1IF
EXIF
ICIF
TCIF
“ 1” means interrupt request, and “ 0” means no interrupt occurs.
• Bit 7 (CMP4IF) Status changed interrupt flag. Set as change occurred in the output of Comparator
CO4, and reset by software.
• Bit 6 (CMP3IF) Status changed interrupt flag. Set as change occurred in the output of Comparator
CO3, and reset by software.
• Bit 5 (CMP2IF) Status changed interrupt flag. Set as change occurred in the output of Comparator
CO2, and reset by software.
• Bit 4 (CMP1IF) Status changed interrupt flag. Set as change occurred in the output of Comparator
CO1, and reset by software.
• Bit 3 Unemployed, read as ‘ 0’ ;
• Bit 2 (EXIF) External interrupt flag. Set by on /INT pin, and reset by software.
• Bit 1 (ICIF) Port 5 input status changed interrupt flag. Set when Port 5 input changes, and reset by
software.
• Bit 0 (TCIF) TCC overflowing interrupt flag. Set when TCC overflows, and reset by software.
• RF can be cleared by instruction but cannot be set.
• IOCF0 is the relative interrupt mask register.
15. R10 ~ R3F
• All of these are the 8-bit general purpose registers.
This specification is subject to change without prior notice.
17
07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
