EM78P257
OTP ROM
4.2 Special Purpose Registers
1. A (Accumulator)
• Internal data transfer, or instruction operand holding
• It can not be addressed.
2. CONT (Control Register)
7
6
5
4
3
-
2
1
0
INTE
INT
TS
TE
PSR2
PSR1
PSR0
• Bit 7 (INTE) INT signal edge
0: interrupt occurs at the rising edge on the INT pin
1: interrupt occurs at the falling edge on the INT pin
• Bit 6 (INT) Interrupt enable
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
• Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
• Bit 4 (TE) TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin\
• Bit 3 Not used.
• Bit 2 (PSR2) ~ Bit 0 (PSR0) TCC prescaler bits.
PSR2
PSR1
PSR0
TCC Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
• The CONT register is both readable and writable.
• Bit 6 is read only.
3. IOC50 ~ IOC70 (I/O Port Control Registers)
• "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.
• Only the higher 2 bits of IOC5 can be defined. (for EM78P257B only)
• Only the lower 2 bits of IOC7 can be defined, the others bits are not available.
This specification is subject to change without prior notice.
18
07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
