EM78P257
OTP ROM
Address
R PAGE registers
IOCX0 PAGE registers
IOCX1 PAGE registers
Reserve
R0
R1
R2
R3
R4
R5
R6
R7
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
(Indirect Addressing Register)
(Time Clock Counter)
(Program Counter)
(Status Register)
(RAM Select Register)
(Port5)
Reserve
CONT (Control Register)
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
IOC50
IOC60
IOC51
(TCCA Counter)
(I/O Port Control Register)
(I/O Port Control Register)
IOC61
IOC71
(Port6)
(TCCBL Counter)
(TCCBH Counter)
(Port7)
IOC70 (I/O Port Control Register)
IOC80 (TCC Control Register)
Reserve
IOC81
IOC91
(TCCC Counter)
(CMPOUT Status Register
& TCC Status Register)
IOC90 (CMP Control Register)
(Low-time Register)
R9
(CO-Input Combine
RA
RB
RC
(TCC Control Register(1))
(TCC Control Register(2))
(TCC Prescaler Register)
IOCA0
IOCA1
IOCB1
(High-time Register)
(Pulse time Register)
sequence)
(Pull-down Control
IOCB0
Register)
(Open-drain Control
IOCC0
Reserve
Reserve
Register)
IOCD0
IOCE0
(Pull-high Control Register)
(WDT Control Register)
RD
RE
(IR Control Register)
(Mouse Control Register)
Reserve
Reserve
(Interrupt Status Register)
RF
IOCF0
(Interrupt Mask Register)
10
1F
General Registers
20
：
Bank0
Bank1
3F
Fig. 5 Data memory configuration
4. R3 (Status Register)
7
6
5
4
T
3
2
Z
1
0
RST
IOCS
PS0
P
DC
C
• Bit 7 (RST) Bit for reset type.
Set to 1 if wake-up from sleep on pin change or comparator status change.
Set to 0 if wake-up from other reset types
This specification is subject to change without prior notice.
13
07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
