EM78P257
OTP ROM
4.7 Timer/Counter
1. Overview
Timer1 (TCCA ) and Timer3 (TCCC) are eight-bit clock counters. Timer2 (TCCB) is a 16-bit clock counter. TCCA,
TCCB, and TCCC can be read and written, and cleared at every reset condition.
2. Function Description
Fig.14 shows the TIMER block diagram. Each signal and block is described as follows:
Set predict value
Set predict value
Set predict value
TCCCEN
Set TCCCIF
TCCAEN
TCCBEN
Set TCCBIF
Set TCCAIF
TCCC
TCCB
TCCA
Overflow
Overflow
Overflow
Osci input or
External input
Osci input or
External input
Osci input or
External input
Fig. 14 TIMER Block Diagram
• Osci input : Input clock.
• TCCX: Timer 1~3 register; TCCX increases until it matches with zero, and then reload the previous
value. If TCCXIE is enabled, TCCXIF will be set at the same time.
3. Programming the Related Registers
When defining TCCX, refer to the related registers of its operation as shown in the Table 10 and Table 11 below.
Table 10 Related Control Registers of the TCCX
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
0x0A
0x0B
TCR(1)/RA
TCR(2)/RB
0
0
0
0
0
0
0
TCCAIE/0 TCCATS/0 TCCATE/0
TCCCIE/0 TCCCTS/0 TCCCTE/0
TCCBIE/0 TCCBTS/0 TCCBTE/0
0x08 TCCCR/IOC80 TCC2E TCC4E
TCC6E
TCCBE
0
0
0
Table 11 Related Status/Data Registers of TCCX
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x09
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
TCCSR/R9 CMPOUT4 CMPOUT3 CMPOUT2 CMPOUT1
TCCA/IOC51 TCCA7 TCCA6 TCCA5 TCCA4
TCCBL/IOC61 TCCBL7 TCCBL6 TCCBL5 TCCBL4 TCCBL3 TCCBL2 TCCBL1 TCCBL0
TCCBH/IOC71 TCCBH7 TCCBH6 TCCBH5 TCCBH4 TCCBH3 TCCBH2 TCCBH1 TCCBH0
0
TCCCIF
TCCA2
TCCBIF TCCAIF
TCCA1 TCCA0
TCCA3
TCCC/IOC81
LTR/IOC91
HTR/IOCA1
PTR/IOCB1
TCCC7
LTR7
HTR7
PTR7
TCCC6
LTR6
HTR6
PTR6
TCCC5
LTR5
HTR5
PTR5
TCCC4
LTR4
HTR4
PTR4
TCCC3
LTR3
HTR3
PTR3
TCCC2
LTR2
HTR2
PTR2
TCCC1
LTR1
TCCC0
LTR0
HTR1
PTR1
HTR0
PTR0
This specification is subject to change without prior notice.
42
07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
