EM78P257
OTP ROM
4.6 Interrupt
The EM78P257A/B has five interrupt sources as listed below:
(1) TCC overflow interrupt.
(2) Port 5 Input Status Changed Interrupt.
(3) External interrupt [(P60, /INT) pin].
(4) Comparators status change.
(5) IR OUT interrupt.
Before the Port 5 Input Status Change Interrupt is enabled, reading Port 5 (e.g. "MOV R5,R5") is necessary. Each
Port 5 pin will have this feature if its status changes The Port 5 Input Status Change Interrupt will wake up the
EM78P257A/B from the sleep mode if it is enabled prior to going into the sleep mode by executing SLEP
instruction. When wake-up occurs, the controller will continue to execute program in-line if the global interrupt is
disabled. . If the global interrupt is enabled, it will branch out to the interrupt vector 3FEH.
RF is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF0 is an interrupt
mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Once
in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The
interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive
interrupts.
The flag (except ICIF0 bit) in the Interrupt Status Register (RF) is set regardless of the status of its mask bit or the
execution of ENI. Note that the outcome of RF will be the logic AND of RF and IOCF0 (refer to Fig.12), The RETI
instruction ends the interrupt routine and enables the global interrupt (the execution of ENI).
When an interrupt is generated by the Timer clock/counter (when enabled), the next instruction will be fetched
from address 3FA,3F8,3F6, and 3F4H(TCC,TCCA,TCCB, and TCCC). When an interrupt is generated by the
Comparators (when enabled), the next instruction will be fetched from address 3F2,3F0,3EE, or 3ECH
individually(CO1,CO2,CO3, or CO4). Before the interrupt subroutine is executed, the contents of ACC and the R3
register will be saved by hardware. If another interrupt occurred, the ACC and R3 will be replaced by the new
interrupt. After the interrupt service routine is finished, ACC and R3 will be pushed back.
This specification is subject to change without prior notice.
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07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
