EM78P257
OTP ROM
Address Name
X: not used.
Reset Type
Wake-Up from Pin
Change
Bit 7
P
Bit 6
P
Bit 5
P
Bit 4
P
Bit 3
P
Bit 2
P
Bit 1
P
Bit 0
P
U: unknown or don’ t care.
P: previous value before reset.
t: check Table 6
2. /RESET Configure
Refer to Fig.11 When the RESET bit in the OPTION word is programmed to 0, the external /RESET is enabled.
When programmed to 1, the internal /RESET is enabled, tied to the internal Vdd and the pin is defined as P71.
VDD
D
Q
CLK
Oscillator
CLK
CLR
Power-On Reset
Voltage Detector
ENWDTB
WDT Timeout
Reset
Setup time
WDT
/RESET
Fig. 11 Block Diagram of Reset of Controller
3. The status of RST, T, and P of STATUS register
A RESET condition is initiated by one of the following events:
1. A power-on condition.
2. A high-low-high pulse on the /RESET pin, or
3. Watchdog timer time-out.
The values of RST, T, and P, as listed in Table 7 below. are used to check how the processor wakes up.
Table 8 shows the events which may affect the status of RST, T, and P.
This specification is subject to change without prior notice.
38
07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
