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EM78860 参数 Datasheet PDF下载

EM78860图片预览
型号: EM78860
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-BIT MICRO-CONTROLLER]
分类和应用: 微控制器
文件页数/大小: 25 页 / 127 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78860  
8-BIT MICRO-CONTROLLER  
It is very important to save ACC,R3 and R5 when processing a interruption.  
Address  
Instruction  
Note  
0x08  
0x09  
0x0A  
0x0B  
0x0C  
0x0D  
0x0E  
:
:
:
:
:
:
:
:
DISI  
;Disable interrupt  
;Save ACC  
MOV A_BUFFER,A  
SWAP A_BUFFER  
SWAPA 0x03  
MOV R3_BUFFER,A  
MOV A,0x05  
MOV R5_BUFFER,A  
:
;Save R3 status  
;Save ROM page register  
:
MOV A,R5_BUFFER  
MOV 0X05,A  
SWAPA R3_BUFFER  
MOV 0X03,A  
SWAPA A_BUFFER  
RETI  
;Return R5  
;Return R3  
;Return ACC  
Instruction Set  
Instruction set has the following features:  
(1). Every bit of any register can be set, cleared, or tested directly.  
(2). The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register.  
The symbol “R” represents a register designator which specifies which one of the 64 registers (including  
operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4  
determine the selected register bank. “b’’ represents a bit field designator which selects the number of the  
bit, located in the register “R’’, affected by the operation. “k’’ represents an 8 or 10-bit constant or literal  
value.  
INSTRUCTION BINARY  
HEX  
MNEMONIC  
OPERATION  
STATUS  
AFFECTED  
None  
C
None  
T,P  
0
0
0
0
0
0
0
0
0
0
0000 0000 0000  
0000 0000 0001  
0000 0000 0010  
0000 0000 0011  
0000 0000 0100  
0000 0000 rrrr  
0000 0001 0000  
0000 0001 0001  
0000 0001 0010  
0000 0001 0011  
0000  
0001  
0002  
0003  
0004  
000r  
0010  
0011  
0012  
0013  
NOP  
No Operation  
Decimal Adjust A  
A CONT  
0 WDT, Stop oscillator  
0 WDT  
A IOCR  
Enable Interrupt  
Disable Interrupt  
[Top of Stack] PC  
[Top of Stack] PC  
Enable Interrupt  
CONT A  
IOCR A  
R2+A R2 bits 9,10 do not clear  
A R  
DAA  
CONTW  
SLEP  
WDTC  
IOW R  
ENI  
DISI  
RET  
RETI  
T,P  
None  
None  
None  
None  
None  
None  
None  
Z,C,DC  
None  
Z
0
0
0
0
0
0
0
0
0000 0001 0100  
0000 0001 rrrr  
0000 0010 0000  
0000 01rr rrrr  
0000 1000 0000  
0000 11rr rrrr  
0001 00rr rrrr  
0001 01rr rrrr  
0014  
001r  
0020  
00rr  
0080  
00rr  
01rr  
01rr  
CONTR  
IOR R  
TBL  
MOV R,A  
CLRA  
CLR R  
0 A  
0 R  
Z
SUB A,R  
SUB R,A  
R-A A  
R-A R  
Z,C,DC  
Z,C,DC  
* This specification are subject to be changed without notice.  
16  
6.24.1998  
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