EM78860
8-BIT MICRO-CONTROLLER
Once the RESET occurs, the following functions are performed.
• The oscillator is running, or will be started.
• The Program Counter (R2) is set to all “0”.
• When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared.
• The Watchdog timer and prescaler are cleared.
• The Watchdog timer is disabled.
• The CONT register is set to all “1”
• The other register (bit7..bit0)
R5 = “00000000”
R6 = PORT
IOC6 = “11111111”
R7 = PORT
IOC7 = “11111111”
R8 = PORT
IOC8 = “11111111”
R9 = PORT
IOC9 = “11111111”
RA = “010x0xxx
RB = “11111111”
RC = “00000000”
RD = “xxxxxxxx”
RE = “00000000”
RF = “00000000”
IOCA = “00000000”
Page0 IOCB = “00000000”
Page0 IOCC = “0xxxxxxx”
Page0 IOCD = “00000000”
Page0 IOCE = “00000000”
IOCF = “00000000”
Page1 IOCB = “00000000”
Page1 IOCC = “00000000”
Page1 IOCE = “00000000”
The controller can be awakened from SLEEP mode or IDLE mode (execution of “SLEP” instruction, named as
SLEEP MODE or IDLE mode) by (1)TCC time out (IDLE mode only) (2) WDT time-out (if enabled) or, (3)
external input at PORT9 . The three cases will cause the controller wake up and run from next instruction in IDLE
mode , reset in SLEEP mode . After wake-up , user should control WATCH DOG in case of reset in GREEN
mode or NORMAL mode. The last two should be open RE register before into SLEEP mode or IDLE mode .
The first one case will set a flag in RF bit0 . And it will go to address 0x08 when TCC generate a interrupt .
Interrupt
The chip has internal interrupts which are falling edge triggered, as followed : TCC timer overflow interrupt
(internal) , two 8-bit counters overflow interrupt .
If these interrupt sources change signal from high to low , then RF register will generate ‘1’ flag to corresponding
register if you enable IOCF register.
RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask
register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the
interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in
the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the RF register.
The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling
interrupts to avoid recursive interrupts.
There are four external interrupt pins including INT0 , INT1 , INT2 , INT3 . And four internal counter interrupt
available.
External interrupt INT0 , INT1 , INT2 , INT3 signals are from PORT7 bit0 to bit3 . If IOCF is enable then these
signal will cause interrupt , or these signals will be treated as general input data .
After reset, the next instruction will be fetched from address 000H and the instruction inturrept is 001H and the
hardware inturrept is 008H.
TCC will go to address 0x08 in GREEN mode or NORMAL mode after time out. And it will run next
instruction from “SLEP” instruction and then go to address 0x08 in IDLE mode . These three cases will
set a RF flag.
* This specification are subject to be changed without notice.
6.24.1998 15
ELAN [ ELAN MICROELECTRONICS CORP ]
