EM78815
8-Bit Microcontroller
Legend: addr: address
b: bit
i: Table pointer control
k: constant
p: special file register (0h~1Fh)
r: File Register
Instruction
Status
Affected
Binary Instruction
Hex
Mnemonic
Operation
Cycle
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0000 rrrr
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
0000
0001
0002
0003
0004
000r
0010
0011
0012
NOP
DAA
No Operation
None
C
1
1
1
1
1
1
1
1
2
Decimal Adjust A
A → CONT
CONTW
SLEP
WDTC
IOW R
ENI
None
T, P
0 → WDT, Stop oscillator
0 → WDT
T, P
None
None
None
None
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
DISI
RET
[Top of Stack] → PC
Enable Interrupt
0 0000 0001 0011
0013
RETI
None
2
0 0000 0001 0100
0 0000 0001 rrrr
0014
001r
CONTR
IOR R
None
None
1
1
CONT → A
IOCR → A
R2 + A → R2 bits
9, 10 do not clear
0 0000 0010 0000
0020
TBL
Z, C, DC
2
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0 0101 01rr rrrr
0 0101 10rr rrrr
0 0101 11rr rrrr
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
MOV R,A
CLRA
None
1
A → R
Z
1
0 → A
CLR R
Z
1
0 → R
SUB A,R
SUB R,A
DECA R
DEC R
Z, C, DC
1
R-A → A
Z, C, DC
1
R-A → R
Z
1
R-1 → A
Z
1
R-1 → R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
Z
1
A ∨ R → A
A ∨ R → R
A & R → A
A & R → R
A ⊕ R → A
A ⊕ R → R
A + R → A
A + R → R
R → A
Z
1
Z
1
Z
1
Z
1
Z
1
Z, C, DC
1
Z, C, DC
1
Z
1
Z
Z
1
R → R
1
/R → A
Z
1
1
/R → R
Z
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
Z
1
DJZA R
DJZ R
None
None
2 if skip
2 if skip
R(n) → A(n-1)
R(0) → C, C → A(7)
R(n) → R(n-1)
R(0) → C, C → R(7)
R(n) → A(n+1)
R(7) → C, C → A(0)
R(n) → R(n+1)
R(7) → C, C → R(0)
0 0110 00rr rrrr
0 0110 01rr rrrr
0 0110 10rr rrrr
0 0110 11rr rrrr
06rr
06rr
06rr
06rr
RRCA R
RRC R
RLCA R
RLC R
C
C
C
C
1
1
1
1
62 •
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)