EM78815
8-Bit Microcontroller
Bit 1 (UTBE) : UART transfer buffer empty flag. Set to 1 when transfer buffer is
empty. Reset to 0 automatically when writing into the UART data
buffer.
Bit 2 (FMERR) : Receiver error flag . Set to 1 when frame error occurs. Clear this bit
to 0 by software.
Bit 3 (OVERR) : Receiver error flag . Set to 1 when over running error occurs. Clear
this bit to 0 by software.
Bit 4 (PRERR) : Receiver error flag . Set to 1 when parity error occurs. Clear this bit
to 0 by software.
Bit 5 (PRE) : Enable parity addition
1 → Enable
0 → Disable
Bit 6(EVEN) : EVEN/ODD parity check select
1 → Even parity
0 → Odd parity
In Universal Asynchronous Receiver Transmitter (UART), each transmitted or
received character is individually synchronized by framing it with a start bit and stop
bit.
The figure below shows the general format of one character sent or received. The
communication channel is normally held in the mark state (high). Character
transmission or reception starts with a transition to the space state (low).
The first bit transmitted or received is the start bit (low). It is followed by the data bits,
in which the least significant bit (LSB) comes first. The data bits are followed by the
parity bit. If present, then the stop bit or bits (high) confirm the end of the frame.
In receiving, the UART synchronizes on the falling edge of the start bit. When two or
more “0” are detected during 3 samples, it is recognized as normal start bit and the
receiving operation is started.
Idle state
(mark)
START
bit
Parity STOP
D0
D1
D2
Dn
bit
bit
1 bit
7 or 8 bits
1 bit
1 bits
One character or frame
Fig. 8 UART Data Frame
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
17
ELAN [ ELAN MICROELECTRONICS CORP ]
