EM78815
8-Bit Microcontroller
3. The parity bit and the stop bit are received.
After one character is received, the UART generates a UART interrupt (if enabled).
URBF bit will be set to 1.
4. The UART makes the following checks:
(a) Parity check: The number of 1 in receive data must match the even or odd
parity setting of the EVEN bit in the UARTSTA register.
(b) Frame check: The start bit must be 0 and the stop bit must be 1.
(c) Overrun check: URBF bit of UARTCON register must be cleared (which means
that the UARTRx register should be read out) before the next received data is
loaded into the UARTRx register.
If any checks failed, a UART interrupt will be generated (if enabled). The error flag
should be cleared by software else a UART interrupt will occur when the next byte
is received.
5. Read received data from the UART register. URBF bit will be cleared by
hardware.
Baud rate
Fsystem
generator
RXE
TXE
RX Control
Interrupt
Control
TX Control
RXD
RX shift register
Parity control
TXD
URR7~URR0
URT8 URT7~URT0
URR8
Error flag
Data Bus
UINVEN
UINVEN
Fig. 10 UART Function Block
Bit 7 : Unused
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
19
ELAN [ ELAN MICROELECTRONICS CORP ]
