EM78808
8-bit Micro-controller
VII.7 Instruction Set
Instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O
register.
The symbol "R" represents a register designator which specifies which one of the 64 registers (including
operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4
determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit,
located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY
HEX
MNEMONIC
OPERATION
STATUS
AFFECTED
None
C
None
T,P
Instruction
cycle
0
0
0
0
0
0
0
0
0
0
0000 0000 0000
0000 0000 0001
0000 0000 0010
0000 0000 0011
0000 0000 0100
0000 0000 rrrr
0000 0001 0000
0000 0001 0001
0000 0001 0010
0000 0001 0011
0000 NOP
0001 DAA
0002 CONTW
0003 SLEP
0004 WDTC
000r IOW R
0010 ENI
0011 DISI
0012 RET
0013 RETI
No Operation
1
1
1
1
1
1
1
1
2
2
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
T,P
None
None
None
None
None
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC
Enable Interrupt
CONT → A
IOCR → A
0
0
0
0000 0001 0100
0000 0001 rrrr
0000 0010 0000
0014 CONTR
001r IOR R
0020 TBL
None
None
Z,C,DC
1
1
2
R2+A → R2 bits 9,10 do
not clear
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000 01rr
0000 1000 0000
rrrr
00rr
0080 CLRA
MOV R,A
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A → R
0 → A
0 → R
R-A → A
R-A → R
R-1 → A
R-1 → R
A ∨ R → A
0000 11rr
0001 00rr
0001 01rr
0001 10rr
0001 11rr
0010 00rr
0010 01rr
0010 10rr
0010 11rr
0011 00rr
0011 01rr
0011 10rr
0011 11rr
0100 00rr
0100 01rr
0100 10rr
0100 11rr
0101 00rr
0101 01rr
0101 10rr
0101 11rr
0110 00rr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
06rr
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
A ∨ R → R
A & R → A
A & R → R
A ⊕ R → A
A ⊕ R → R
A + R → A
A + R → R
R → A
R → R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1)
R(0) → C, C → A(7)
R(n) → R(n-1)
1
1
1
1
INCA R
INC R
DJZA R
DJZ R
1
None
None
C
2 if skip
2 if skip
1
RRCA R
0
0110 01rr
rrrr
06rr
RRC R
C
1
______________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
8/1/2004 (V3.1)
46
ELAN [ ELAN MICROELECTRONICS CORP ]
