EM78468
8-BIT Microcontroller
4.1 Operational Registers
4.1.1
R0/IAR (Indirect Addressing Register)
(Address: 00h)
R0 is not a physically implemented register. It is used as indirect addressing pointer. Any
instruction using R0 as register actually accesses the data pointed by the RAM Select
Register (R4).
4.1.2
R1/TCC (Time Clock /Counter)
(Address: 01h)
Increases by an external signal edge applied to TCC, or by the instruction cycle clock.
Written and read by the program as any other register.
4.1.3
R2/PC (Program Counter)
(Address: 02h)
* The structure is depicted in Fig. 3
* Generates 4K × 13 on-chip ROM addresses to the relative programming instruction
codes.
* "JMP" instruction allows direct loading of the low 10 program counter bits.
* "CALL" instruction loads the low 10 bits of the PC and PC+1, then push it into the stack.
* "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the
top of stack.
* "MOV R2, A" allows the loading of an address from the A register to the PC. The
contents of the ninth and tenth bits do not change.
* "ADD R2, A" allows a relative address be added to the current PC.
* The most significant bit (A10~A11) will be loaded with the content of bits PS0~PS1 in
the Status register (R3) upon execution of a "JMP'' or "CALL'' instruction.
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Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
