EM77950
BB Controller
18 Instruction Description
18.1 Instruction Set Summary
Status
Type
Binary Instruction
Mnemonic
Operation
No operation
Cycles
Affected
None
None
None
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
NOP
1
1
1
WDTC
RET
WDT ← 0
PC ← (Top of Stack)
PC ← (Top of Stack);
Enable Interrupt
WDT ← 0
None
None
0000
0000
0000
0000
0000
0000
0011
0100
RETI
1
1
System
Control
SLEP
Stop oscillator
None
None
C
0000
0000
0000
0000
0000
0000
0000
0000
0000
0101
0110
0111
ENI
Enable Interrupt
Disable Interrupt
Decimal Adjust A
1
1
1
DISI
DAA
r ← ROM[(TABPT[15:1])]
TABPT ← TABPT+1
r ← ROM[(TABPT[15:1])]
None
None
None
1010
1010
1010
0000
0001
0010
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
TBRDP r
TBRD r
2
2
2
r ← ROM[(TABPT[15:1])]
TABPT ← TABPT-1
TBRDM r
A ← ROM[(TABPT[15:1])]
TABPT ← TABPT+1
A ← ROM[(TABPT[15:1])]
A ← ROM[(TABPT[15:1])]
TABPT ← TABPT-1
R2 ← R2+A
None
None
0000
0000
0000
0011
1010
0000
0000
0000
1101
1011
0000
0000
0000
0000
kkkk
1010
1011
1100
0010
kkkk
TBRDP A
TBRD A
TBRDM A
TBL
2
2
2
1
1
Table
Look up
None
C, DC, Z
None
A ← k
PC ← [Top of Stack]
RETL #k
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
rrrr
rrrr
rrrr
rrrr
OR A, r
A ← A .or. r
r ← r .or. A
A ← A .or. k
A ← A .and. r
r ← r .and. A
A ← A .and. k
A ← A .xor. r
r ← r .xor. A
A ← A .xor. k
A ← /r
1
1
1
1
1
1
1
1
1
1
1
OR r, A
kkkk
Rrrr
Rrrr
kkkk
Rrrr
rrrr
kkkk
rrrr
OR A, #k
AND A, r
AND r, A
AND A, #k
XOR A, r
XOR r, A
XOR A, #k
COMA r
COM r
rrrr
kkkk
rrrr
rrrr
kkkk
rrrr
kkkk
rrrr
Logic
rrrr
rrrr
r ← /r
[C,r] rotate right k bits to
[C,A]
[C,r] rotate right k bits to
[C,r]
C
C
1011
1011
00kk
01kk
rrrr
rrrr
rrrr
rrrr
RRCA r, #k
RRC r, #k
1
1
[C,r] rotate left k bits to
[C,A]
[C,r] rotate left k bits to [C,r]
C
C
1011
1011
0101
10kk
11kk
10kk
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
RLCA r, #k
RLC r, #k
1
1
1
[C,r] shift right k bits to A
Insert C into high order bits
[C,r] shift left k bits to A
Insert C into low order bits
None
SHRA r, #k
None
0101
11kk
rrrr
rrrr
SHLA r, #k
1
88 •
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)