EM77950
BB Controller
16.3 PLL Oscillator
The Phase-locked loop (PLL) technology is employed to produce four different
frequencies: 6 MHz, 12MHz, 24MHz and 48 MHz (external 6MHz crystal). Setting the
SYS_CLK bits can select the system clock source. PLL is enabled except when
entering Green and Sleep mode.
16.4 Selected PLL Oscillation out
As shown in register FRCC (0x94), EM77950 can output the selected PLL frequency
divided by the prescaler. Once the pin is enabled as a PLL clock out, the output
frequency can be implemented by the peripherals of the chip. If disabled, this pin is
used as pin PF0, a general purpose I/O pin.
17 Low-Power Mode
17.1 Introduction
The EM77950 has two power-saving modes, green mode and sleep mode. Figure 17
shows the mode change diagram.
Power On
Normal
1. Key Wake-up
2. WDT Time out
3. /Reset
WDTC[7].Green=0
SLEP INST.
1. WDTC[7].Green=1
2. WDT Time out
3. /Reset
Key Wake up
Green
Sleep
SLEP INST.
Fig. 17 Three-Mode State
86 •
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
