EM77950
BB Controller
7.1.23 PWM Duty Latch – DL0L (0x25)/DL0H (0x26) & DL1L
(0x2B)/DL1H (0x2C)
R26 : R25 16-bit PWM0 output duty cycle buffer. R2C : R2B 16-bit PWM1 output duty
cycle buffer.
7.1.24 BB Address Register – RFAAR (0x2D)
Register R2D indicates BB indirect RAM address.
7.1.25 BB Data Buffer Register – RFDB (0x2E)
Register R2E indicates BB indirect RAM data.
7.1.26 BB Data Read/Write Control Register – RFACR (0x2F)
Register R2F indicates BB RAM access control.
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
RRST
RFRD
RFWR
Bit 0 (RFWR): Write BB register.
Bit 1 (RFRD): Read BB register
Bit 2 (RRST): BB S/W reset.
Bit 3 ~ Bit 7: reserved
7.1.27 BB Interrupt Flag Register – RFINTF (0x30)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CSDF TX_AEF RX_AFF TX_ EMPTYF RX_OFF LINK_ DISF LOCK_OUTF LOCK_ INF
Bit 0 (LOCK_INF): This bit reflects the LOCK IN flag interrupt.
Bit 1 (LOCK_OUTF): This bit reflects the LOCK OUT flag interrupt.
Bit 2 (LINK_DISF): This interrupt is invoked by the zero counter capacitor discharge
mechanism.
Bit 3 (RX_OFF): This bit reflects the RX FIFO full flag interrupt.
Bit 4 (TX_EMPTYF): This bit reflects the TX EMPTY flag interrupt.
Bit 5 (RX_AFF): This bit reflects the RX FIFO almost full flag interrupt.
Bit 6 (TX_AEF): This bit reflects the TX FIFO almost empty flag interrupt.
Bit 7 (CSDF): This flag indicates that a carrier-sense interrupt has occurred.
30 •
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
