欢迎访问ic37.com |
会员登录 免费注册
发布采购

EM65570AGH 参数 Datasheet PDF下载

EM65570AGH图片预览
型号: EM65570AGH
PDF下载: 下载PDF文件 查看货源
内容描述: 68COM / 98SEG 65K色STN LCD驱动器 [68COM / 98SEG 65K Color STN LCD Driver]
分类和应用: 驱动器
文件页数/大小: 100 页 / 928 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
 浏览型号EM65570AGH的Datasheet PDF文件第61页浏览型号EM65570AGH的Datasheet PDF文件第62页浏览型号EM65570AGH的Datasheet PDF文件第63页浏览型号EM65570AGH的Datasheet PDF文件第64页浏览型号EM65570AGH的Datasheet PDF文件第66页浏览型号EM65570AGH的Datasheet PDF文件第67页浏览型号EM65570AGH的Datasheet PDF文件第68页浏览型号EM65570AGH的Datasheet PDF文件第69页  
EM65570  
68COM/ 98SEG 65K Color STN LCD Driver  
When writing to the control register, it is used directly by addressing D7~D4 of the data  
bus. When reading, you must first set the RA register for the specific register address  
before you can read specific register. Therefore, a 2-step procedure is required to  
perform a read register operation. After reading, the specific register will output to  
D3~D0 of the data bus. All nibbles, except D3~D0, of the data bus are all “H.” Access  
to undefined register address area is prohibited. When RS is “L,” all read/write  
operations are accessed to display RAM. Then the data bus does not include the  
register address. When writing, D3~D0 data is written to the register designated at  
D7~D4 on the rising edge of the WRB signal. When reading, the register can output to  
data bus during RDB active period. The control register and display RAM have equal  
access sequence  
8.2.1 X Address Register (AX)  
D7 D6 D5 D4 D3 D2 D1 D0  
AX3 AX2 AX1 AX0  
(At the time of reset: {AX3, AX2, AX1, AX0} = 0H, read address: 0H)  
CSB RS RDB WRB RE2 RE1 RE0  
0
0
0
0
0
1
1
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0  
AX7 AX6 AX5 AX4  
CSB RS RDB WRB RE2 RE1 RE0  
0
0
0
1
0
1
1
0
0
0
0
(At the time of reset: {AX7, AX6, AX5, AX4} = 0H, read address: 1H)  
The AX register is set to the X-direction address of display RAM. In data setting,  
command is divided into lower and upper sections at 4-bit of data each in order to  
accommodate the required 8-bit of total data.  
8.2.2 Y Address Register (AY)  
D7 D6 D5 D4 D3 D2 D1 D0  
AY3 AX2 AY1 AY0  
(At the time of reset: {AY3, AY2, AY1, AY0} =0H, read address: 2H)  
CSB RS RDB WRB RE2 RE1 RE0  
0
0
1
0
0
1
1
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0  
AY6 AY5 AY4  
CSB RS RDB WRB RE2 RE1 RE0  
0
0
1
1
0
1
1
0
0
0
0
*
* Don’t Care  
(At the time of reset: {AY6, AY5, AY4} =0H, read address: 3H)  
The AY register is set to the Y-direction address of display RAM. In data setting,  
command is divided into lower and upper sections at 4-bit and 3-bit of data respectively  
in order to accommodate the required 7-bit total data. 00H to 43H are applicable to the  
values for AY6 to AY0, but 44H to FFH are not applicable.  
Product Specification (V1.0) 09.05.2005  
(This specification is subject to change without further notice)  
59  
 复制成功!