HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Clock Suspend Mode
t
t
CES
t
CES
CEH
8
0
1
2
3
4
5
6
7
9
10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
Read cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
CS
RAS
= V or V
IH
IL
CAS
WE
BS
Address
R:a
C:a
R:b
C:b
DQM,
DQMU/DQML
DQ (output)
DQ (input)
a
a+1 a+2
a+3
b
b+1 b+2 b+3
High-Z
Bank0 Active clock
Active suspend start
Active clock Bank0
suspend end Read
Bank3 Read suspend Read suspend
Bank0
Earliest Bank3
Precharge
Bank3
Active
start
end Read Precharge
CKE
Write cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
CS
RAS
= V or V
IH
IL
CAS
WE
BS
R:b
a+1
Address
DQM,
DQMU/DQML
DQ (output)
DQ (input)
R:a
C:a
a
C:b
High-Z
a+2
a+3
b
b+1 b+2 b+3
Bank0
Active clock Bank0 Bank3 Write suspend Write suspend Bank3
Earliest Bank3
Precharge
Bank0 Active clock
Active suspend start
Precharge
end Write
supend end Write Active
start
Data Sheet E0082H10
60