EDS6432AFTA, EDS6432CFTA
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6432AF]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6432CF]
-6B
-75
Parameter
Symbol
tCK
min.
max.
—
min.
max.
—
Unit
ns
Notes
1
System clock cycle time
(CL = 2)
10
10
(CL = 3)
tCK
tCH
tCL
tAC
tOH
tLZ
6
—
7.5
2.5
2.5
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
CLK high pulse width
2.5
2.5
—
2
—
—
1
CLK low pulse width
—
—
1
Access time from CLK
Data-out hold time
5.4
—
5.4
—
1, 2
1, 2
1, 2, 3
1, 4
1
2
CLK to Data-out low impedance
CLK to Data-out high impedance
Input setup time
0
—
0
—
tHZ
tSI
—
1.5
0.8
60
42
5.4
—
—
5.4
—
1.5
0.8
67.5
45
Input hold time
tHI
—
—
1
Ref/Active to Ref/Active command period
tRC
tRAS
—
—
1
Active to Precharge command period
120000
120000
1
Active command to column command
(same bank)
Precharge to active command period
Write recovery or data-in to precharge lead
time
tRCD
tRP
18
18
12
—
—
—
20
20
15
—
—
—
ns
ns
ns
1
1
1
tDPL
2CLK +
18ns
2CLK +
20ns
Last data into active latency
tDAL
—
—
Active (a) to Active (b) command period
Transition time (rise and fall)
tRRD
tT
12
—
5
15
—
5
ns
ns
1
0.5
0.5
Refresh period
(4096 refresh cycles)
tREF
—
64
—
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V(EDS6432AF)
and 1.2V (EDS6432CF).
2. Access time is measured at 1.4V(EDS6432AF) and 1.2V (EDS6432CF). Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Data Sheet E0487E50 (Ver. 5.0)
7
ELPIDA [ ELPIDA MEMORY ]
