EDS5104ABTA, EDS5108ABTA, EDS5116ABTA
Test Conditions
• Input and output timing reference levels: 1.4V
• Input waveform and output load: See following figures
2.4 V
I/O
2.0 V
input
0.8 V
0.4 V
CL
t
T
tT
Output load
Relationship Between Frequency and Minimum Latency
Parameter
-6B
166
6.0
-7A
133
7.5
-75
Frequency (MHz)
tCK (ns)
Symbol
lRCD
7.5
3
Notes
1
Active command to column command
(same bank)
Active command to active command
(same bank)
3
2
8
6
2
2
lRC
10
7
9
6
3
2
1
1
1
1
Active command to precharge command
(same bank)
lRAS
lRP
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
3
lDPL
2
Active command to active command
(different bank)
lRRD
lSREX
lDAL
2
1
5
2
1
4
2
1
5
1
Self refresh exit time
2
Last data in to active command
(Auto precharge, same bank)
= [lDPL + lRP]
= [lRC]
3
Self refresh exit to command input
lSEC
10
8
9
Precharge command to high impedance
(CL = 2)
lHZP
lHZP
—
3
2
3
2
3
(CL = 3)
Last data out to active command
(Auto precharge, same bank)
lAPR
1
1
1
Last data out to precharge (early precharge)
(CL = 2)
lEP
lEP
—
–1
–2
–1
–2
(CL = 3)
–2
Column command to column command
Write command to data in latency
DQM to data in
lCCD
lWCD
lDID
1
0
0
2
1
2
0
1
1
0
0
2
1
2
0
1
1
0
0
2
1
2
0
1
DQM to data out
lDOD
lCLE
lMRD
lCDD
lPEC
CKE to CLK disable
Register set to active command
/CS to command disable
Power down exit to command input
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Preliminary Data Sheet E0250E10 (Ver. 1.0)
7
ELPIDA [ ELPIDA MEMORY ]
