EDS5104ABTA, EDS5108ABTA, EDS5116ABTA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V 0.3V)
Notes
1, 2, 4
1, 2, 4
Parameter
Symbol
CI1
Pins
CLK
min.
2.5
Typ
—
max.
3.5
Unit
pF
Input capacitance
Address, CKE, /CS, /RAS,
/CAS, /WE, DQM,
CI2
2.5
4
—
—
3.8
6.5
pF
pF
1, 2, 3, 4
Data input/output capacitance
CI/O
DQ
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.
3. DQM = VIH to disable DOUT.
4. This parameter is sampled and not 100% tested.
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 3.3V 0.3V, VSS, VSSQ = 0V)
-6B
-7A
min.
7.5
2.5
2.5
—
-75
min.
7.5
2.5
2.5
—
Parameter
Symbol min.
max.
—
max.
—
max.
—
Unit Notes
System clock cycle time
CLK high pulse width
CLK low pulse width
Access time from CLK
Data-out hold time
tCK
tCH
tCL
tAC
tOH
tLZ
tHZ
tSI
6.0
2.5
2.5
—
ns
ns
1
—
—
—
1
—
—
—
ns
ns
ns
ns
ns
ns
ns
1
5.0
—
5.4
—
5.4
—
1, 2
1, 2
1, 2, 3
1, 4
1
2.5
1
3.0
1
3.0
1
CLK to Data-out low impedance
CLK to Data-out high impedance
Input setup time
—
—
—
—
5.4
—
—
5.4
—
—
5.4
—
1.5
0.8
1.5
0.8
1.5
0.8
Input hold time
tHI
—
—
—
1
Ref/Active to Ref/Active command
period
tRC
60
42
18
18
12
—
60
45
15
15
15
—
67.5
45
—
ns
ns
ns
ns
ns
1
1
1
1
1
Active to Precharge command
period
tRAS
tRCD
tRP
120000
—
120000
—
120000
—
Active command to column
command (same bank)
20
Precharge to active command
period
—
—
20
—
Write recovery or data-in to
precharge lead time
tDPL
tDAL
—
—
15
—
2CLK +
18ns
2CLK +
15ns
2CLK +
20ns
Last data into active latency
—
—
—
Active (a) to Active (b) command
period
tRRD
tT
12
0.5
—
—
5
15
0.5
—
—
5
15
0.5
—
—
5
ns
ns
ms
1
Transition time (rise and fall)
Refresh period
(8192 refresh cycles)
tREF
64
64
64
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
2. Access time is measured at 1.4V. Load condition is CL = 50pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Preliminary Data Sheet E0250E10 (Ver. 1.0)
6
ELPIDA [ ELPIDA MEMORY ]
