EDS5104ABTA, EDS5108ABTA, EDS5116ABTA
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
VIH
Read cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
/CS
/RAS
=
VIH or VIL
/CAS
/WE
BS
Address
DQM
R:a
C:a
R:b
C:b
C:b'
C:b"
DQ (output)
DQ (input)
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3
High-Z
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 3 Bank 0
Bank 3
Read
Bank 3
Read
Bank 3
Precharge
Read
Precharge
VIH
CKE
Write cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
/CS
/RAS
/CAS
/WE
BS
Address
DQM
R:a
C:a
a
R:b
C:b
C:b'
C:b"
High-Z
DQ (output)
DQ (input)
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b" b"+1b"+2 b"+3
Bank 0
Active
Bank 0
Write
Bank 3
Active
Bank 3
Write
Bank 0
Precharge
Bank 3
Write
Bank 3
Write
Bank 3
Precharge
Read/Single Write Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
CLK
V
IH
CKE
/CS
/RAS
/CAS
/WE
BS
R:a
C:a
R:b
C:a' C:a
a
Address
DQM
DQ (input)
DQ (output)
a
a+1 a+2 a+3
a
a+1 a+2 a+3
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 0 Bank 0
Write Read
Bank 0
Precharge
Bank 3
Precharge
V
IH
CKE
/CS
/RAS
/CAS
/WE
BS
R:a
C:a
R:b
C:a
C:b C:c
Address
DQM
a
b
c
DQ (input)
DQ (output)
a
a+1
a+3
Bank 0
Active
Bank 0
Read
Bank 0
Write
Bank 0 Bank 0
Write Write
Bank 0
Precharge
Bank 3
Active
Read/Single write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
=
VIH or VIL
Preliminary Data Sheet E0250E10 (Ver. 1.0)
45
ELPIDA [ ELPIDA MEMORY ]
