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EDS5104ABTA-7A 参数 Datasheet PDF下载

EDS5104ABTA-7A图片预览
型号: EDS5104ABTA-7A
PDF下载: 下载PDF文件 查看货源
内容描述: 512M位的SDRAM [512M bits SDRAM]
分类和应用: 动态存储器
文件页数/大小: 52 页 / 558 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDS5104ABTA, EDS5108ABTA, EDS5116ABTA  
Auto Precharge  
Read with auto-precharge  
In this operation, since precharge is automatically performed after completing a read operation, a precharge  
command need not be executed after each read operation. The command executed for the same bank after the  
execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is  
required before execution of the next command.  
[Clock cycle time]  
/CAS latency  
Precharge start cycle  
3
2
2 cycle before the final data is output  
1 cycle before the final data is output  
CLK  
ACT  
READA  
ACT  
CL=2 Command  
lRAS  
DQ  
out0  
out1  
out2  
out3  
lAPR  
CL=3 Command  
DQ  
ACT  
READA  
ACT  
lRAS  
out0  
out1  
out2  
out3  
lAPR  
Note: Internal auto-precharge starts at the timing indicated by " ".  
And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge  
"
".  
Burst Read (BL = 4)  
Write with auto-precharge  
In this operation, since precharge is automatically performed after completing a burst write or single write operation,  
a precharge command need not be executed after each write operation. The command executed for the same bank  
after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is  
required between the final valid data input and input of next command.  
CLK  
WRITA  
ACT  
ACT  
Command  
DQ  
IRAS  
in0 in1 in2 in3  
lDAL  
Note: Internal auto-precharge starts at the timing indicated by " ".  
and an interval of tRAS (lRAS) is required between previous active (ACT) command  
and internal precharge " ".  
Burst Write (BL = 4)  
Preliminary Data Sheet E0250E10 (Ver. 1.0)  
29  
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