EDS2532CABJ
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
-75
-1A
Parameter
Symbol
tCK
min.
max.
—
min.
max.
—
Unit
ns
Notes
1
System clock cycle time
(CL = 2)
10
10
(CL = 3)
tCK
tCH
tCL
tAC
tOH
7.5
2.5
2.5
—
—
—
—
5.4
—
—
5.4
—
—
10
3
—
—
—
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
CLK high pulse width
CLK low pulse width
Access time from CLK
Data-out hold time
1
3
1
—
2.0
0
1, 2
1, 2
1, 2, 3
1, 4
1
2.0
0
—
—
6
CLK to Data-out low impedance tLZ
CLK to Data-out high impedance tHZ
—
—
2
Input setup time
Input hold time
tSI
tHI
1.5
0.8
—
—
1
1
Ref/Active to Ref/Active
command period
tRC
67.5
45
—
70
50
20
20
20
—
ns
ns
ns
ns
ns
1
1
1
1
1
Active to Precharge command
period
tRAS
tRCD
tRP
120000
—
120000
—
Active command to column
command (same bank)
20
Precharge to active command
period
20
—
—
Write recovery or data-in to
precharge lead time
tDPL
tDAL
tRRD
tT
15
—
—
Last data into active latency
2CLK + 20ns —
2CLK + 20ns —
Active (a) to Active (b) command
period
15
0.5
—
—
20
0.5
—
—
5
ns
ns
ms
1
Transition time (rise and fall)
5.0
64
Refresh period
(4096 refresh cycles)
tREF
64
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.2V.
2. Access time is measured at 1.2V. Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Data Sheet E0460E40 (Ver. 4.0)
7
ELPIDA [ ELPIDA MEMORY ]
