EDS2532CABJ
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol
IDD1
Grade
max.
125
Unit
mA
Test condition
Notes
1, 2, 3
Burst length = 1
tRC = tRC (min.)
Operating current
CKE = VIL,
tCK = tCK (min.)
Standby current in power down IDD2P
3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
6
Standby current in power down
IDD2PS
2
CKE = VIL, tCK = ∞
7
(input signal stable)
Standby current in non power
down
CKE, /CS = VIH,
tCK = tCK (min.)
IDD2N
20
9
4
Standby current in non power
IDD2NS
CKE = VIH, tCK = ∞,
/CS = VIH
8
down (input signal stable)
Active standby current in power
down
CKE = VIL,
tCK = tCK (min.)
IDD3P
4
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
Active standby current in power
IDD3PS
3
CKE = VIL, tCK = ∞
down (input signal stable)
Active standby current in non
IDD3N
CKE, /CS = VIH,
tCK = tCK (min.)
50
30
power down
Active standby current in non
IDD3NS
CKE = VIH, tCK = ∞,
/CS = VIH
power down (input signal stable)
-75
-1A
155
125
tCK = tCK (min.),
BL = 4
Burst operating current
Refresh current
IDD4
IDD5
IDD6
IDD6
-75
-1A
265
255
tRC = tRC (min.)
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
Self refresh current
3
1
Self refresh current
(L-version)
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
-XXL
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Data Sheet E0460E40 (Ver. 4.0)
5
ELPIDA [ ELPIDA MEMORY ]
