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EDS2532CABJ-75L-E 参数 Datasheet PDF下载

EDS2532CABJ-75L-E图片预览
型号: EDS2532CABJ-75L-E
PDF下载: 下载PDF文件 查看货源
内容描述: 256M位的SDRAM [256M bits SDRAM]
分类和应用: 存储内存集成电路动态存储器时钟
文件页数/大小: 48 页 / 637 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDS2532CABJ  
Bank active command interval  
1. Same bank: The interval between the two bank active commands must be no less than tRC.  
2. In the case of different bank active commands: The interval between the two bank active commands must be no  
less than tRRD.  
CLK  
Command  
Address  
BS  
ACT  
ACT  
ROW  
ROW  
tRC  
Bank 0  
Active  
Bank 0  
Active  
Bank Active to Bank Active for Same Bank  
CLK  
Command  
Address  
ACT  
ACT  
ROW:0  
ROW:1  
BS  
tRRD  
Bank 0  
Active  
Bank 3  
Active  
Bank Active to Bank Active for Different Bank  
Mode register set to Bank active command interval  
The interval between setting the mode register and executing a bank active command must be no less than lMRD.  
CLK  
Command  
Address  
MRS  
ACT  
OPCODE  
BS & ROW  
lMRD  
Mode  
Register Set  
Bank  
Active  
Mode register set to Bank active command interval  
Data Sheet E0460E40 (Ver. 4.0)  
36  
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