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EDS2532CABJ-75L-E 参数 Datasheet PDF下载

EDS2532CABJ-75L-E图片预览
型号: EDS2532CABJ-75L-E
PDF下载: 下载PDF文件 查看货源
内容描述: 256M位的SDRAM [256M bits SDRAM]
分类和应用: 存储内存集成电路动态存储器时钟
文件页数/大小: 48 页 / 637 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDS2532CABJ  
Write command to Read command interval:  
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same  
bank as the preceding write command, the read command can be performed after an interval of no less than 1  
clock. However, in the case of a burst write, data will continue to be written until one clock before the read  
command is executed.  
CLK  
Command  
DQM  
WRIT  
in A0  
READ  
DQ (input)  
DQ (output)  
out B0  
out B1  
out B2  
out B3  
Burst Write Mode  
CL = 2  
Column = A  
Write  
/CAS Latency  
Column = B  
Dout  
Column = B  
Read  
BL = 4  
Bank 0  
WRITE to READ Command Interval (1)  
CLK  
WRIT  
in A0  
READ  
Command  
DQM  
DQ (input)  
in A1  
DQ (output)  
out B0  
out B1  
out B2  
out B3  
Burst Write Mode  
CL = 2  
Column = A  
Write  
/CAS Latency  
Column = B  
Read  
Column = B  
Dout  
BL = 4  
Bank 0  
WRITE to READ Command Interval (2)  
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be  
executed; it is necessary to separate the two commands with a precharge command and a bank active  
command.  
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1  
clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will  
continue to be written until one clock before the read command is executed (as in the case of the same bank and  
the same address).  
Data Sheet E0460E40 (Ver. 4.0)  
31  
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